1. Field of the Invention
The present invention relates generally to a data recovery algorithm and a serial link data receiver adopting the same and, more particularly, to an algorithm, which enables a data receiving end for receiving data serially transmitted by a data transmitting end and recovering the data to stably recover data without loss even though seriously distorted data that deviates from the valid window of the data by 50% due to the generations of data skew (i.e., a phenomenon in which a difference occurs in the time that respective bits take to arrive at a termination device. Mainly, the phenomenon occurs due to the difference between the lengths of cables or board lines) and transformation is received, and a serial data receiver adopting the algorithm.
2. Description of the Related Art
Generally, in data transceiving between two devices mounted on a circuit board or digital transceiving between communication devices spaced far apart from each other, when data is serially transmitted and received, there are many advantages in that the compression of the data is easy, the number of device pins can be reduced, a circuit board can be simplified and a signal interference possibly occurring between parallel signals can be prevented, so that a method of serially transceiving digital data has been applied to various systems. Generally, chips referred to as a serial link are operated with a transmitting end and a receiving end forming a pair, and the two chips are connected to each other by a transmission cable. Meanwhile, serial link-series chips that are frequently used for image signal transmission, such as a Low Voltage Differential Swing (LVDS) transceiving chip or a Transition Minimized Differential Signaling (TMDS) transceiving chip, are characterized in that the data transmission and clock transmission between the transceiving chips are performed through different channels. Generally, for data output from a transmission chip, even though the data is synchronized with a clock at the time of output, the skew between the data and the clock may be generated when the data arrives at a receiving end due to various reasons, and further a serious data distortion phenomenon, such as the transformation of a data valid window, may occur. In this case, the pattern of the data is not input in an ideal condition in which the recovery is easy, so that a receiving end chip must be provided with characteristics capable of recovering the data to a normal state in all cases, and a recovery algorithm.
FIG. 3 is a view showing one of conventional circuits for adjusting the above data skew. According to the circuit, when transition exists between adjacent data, the data is recovered in such a way as to detect the edge of the data, compare the positions of the data edge and a reference edge, and adjust the data to be delayed based on the difference between the positions.
With reference to the construction of FIG. 3, the data recovery is described in detail below. First, serial data and a clock signal output from a transmitting end are input to the input buffer 31 and clock buffer 35 of the receiving end 30, respectively, through a data bus or a cable. A clock generator 37 generates a transition clock signal and a central clock signal based on the input clock, and supplies the transition clock signal and the central clock signal to a data sampler 33. Thereafter, the data sampler 33 continuously samples the transition position between two adjacent serial data bits in response to the clock, samples the accurate center position of each data bit, and transmits a result value to an edge comparator 34. The edge comparator 34 compares the sampled value with an ideal logic critical value. If there exists a difference therebetween, it is determined that data skew is generated. In this case, the comparator 34 determines the extent of the data skew according to the magnitude of the difference, generates a skew control signal, and transmits the skew control signal to a data delay cell 32. The data delay cell 32 delays the data in response to the skew control signal to carry out adjustment so that a reference clock is accurately located at the center position of each serial data bit.
There are three major problems in the conventional method. First, since the conventional method is constructed to detect skew existing on current data intended to be recovered and adjust the skew of next input data, there is no way to adjust a data recovery error caused by the skew of the current data. Second, in the case where the data is transformed by skew and transformation by 50% or more, that is, the phase of the data is changed by ½ of a cycle or more, it is difficult to accurately recover data because the extent of the skew cannot be accurately detected. Furthermore, since relatively many additional circuits are required to implement the conventional method, it is problematic in that power consumption increases and the size of a chip increases.